Enabling Terabit capacity optical interconnects requires a paradigm shift in the packaging approach. The electrical interconnect distance between the optical engine (OE) and the digital switching chip must be minimised, removing signal conditioning chips and unwanted components like sockets that would otherwise be required and would inevitably lead to increased power consumption and lower signal integrity. It also requires the right combination of photonic and electronic technology that will be integrated to deliver high performance, low-cost and energy efficient optical engines. This approach has the potential to remove the optical interconnect bandwidth bottlenecks and allow DC networks and the 5G wired infrastructure, which heavily rely on them, to grow. POETICS is a research proposal that targets the development of novel Terabit optical engines and optical switching circuits and to copackage them with digital switching chips to realise Multi-Chip Modules (MCM) with Tb/s capacities, very high energy efficiency that fit into the roadmap of vendors. In order to do so POETICS will utilize SiGe BiCMOS, InP, PolyBoard and TriPleX technologies and rely on hybrid integration, which allows the selection and combination of the best performing components. POETICS in specific targets 1) MCM with 1.6Tb/s OEs based on 8-fold InP-EML arrays (200Gb/s per lane) and PolyBoard with parallel SMFs on par with the PSM/DR spec for 500m-2km intra-DC connectivity. 2) MCM with 1.6Tb/s OEs based on 8-fold InP-EML arrays (200Gb/s per lane) and 3D PolyBoard with duplex MCFs for 5G optical fronthaul applications 3) low power consumption 3D Benes optical switch 4) MCM coherent 64Gbaud OEs with up to 600Gb/s capacity of DC interconnect applications within 80-120 km reach on par with 400G-ZR specification.